1. Field of the Invention
The invention relates in general to a charge recycling method and a driving circuit and a low power memory using the same, and more particularly to a charge recycling method capable of reducing the power consumption, and a driving circuit and a low power memory using the charge recycling method.
2. Description of the Related Art
FIG. 1A (Prior Art) is a schematic illustration showing a Y pre-decode driving circuit 100 of a conventional memory. Referring to FIG. 1A, the Y pre-decode driving circuit 100 includes a first pre-decode driver 101 and a second pre-decode driver 102. The first pre-decode driver 101 includes a first switch Q1 and a second switch Q2. The second pre-decode driver 102 includes a third switch Q3 and a fourth switch Q4. Each pre-decode driver has to drive several corresponding select transistors (not shown) in a Y multiplexer (YMUX) in a memory, so each output node of pre-decode driver corresponds to a parasitic capacitor, the output node YP1 of the first pre-decode driver 101 corresponds to a first parasitic capacitor CAP1 and the output node YP2 of the second pre-decode driver 102 corresponds to a second parasitic capacitor CAP2. In addition, each select transistor in the YMUX substantially corresponds to one bit line.
The first pre-decode driver 101 is controlled by a first address select signal A1 to drive the corresponding select transistors, and the second pre-decode driver 102 is controlled by a second address select signal A2 to drive the corresponding select transistors. FIG. 1B (Prior Art) shows waveforms of time V.S. voltages of the address select signals A1 and A2, the output nodes YP1 and YP2 and the parasitic capacitors CAP1 and CAP2 of the Y pre-decode driving circuit 100. Before the time instant t, the memory controls the second pre-decode driver 102 through the second address select signal A2, and the second pre-decode driver 102 selects the desired bit line in cooperation with a bit line driver (not shown in FIG. 1A). At this time, the second address select signal A2 turns on the third switch Q3 and turns off the fourth switch Q4, the second parasitic capacitor CAP2 is charged to a designed voltage POWER, the first address select signal A1 turns off the first switch Q1 and turns on the second switch Q2, and the voltage level of the first parasitic capacitor CAP1 is the ground voltage GND.
At the time instant t, the memory wants to select a next bit line. Thus, the memory controls the first pre-decode driver 101 through the first address select signal A1, and the first pre-decode driver 101 selects the desired bit line in cooperation with the bit line driver. At this time, the first address select signal A1 turns on the first switch Q1 and turns off the second switch Q2, and the first parasitic capacitor CAP1 is started to be charged until the voltage thereof reaches the designed voltage POWER. Next, the second address select signal A2 turns off the third switch Q3 and turns on the fourth switch Q4, and the second parasitic capacitor CAP2 starts to discharge until the voltage thereof reaches the ground voltage GND.
In the Y pre-decode driving circuit 100 mentioned hereinabove, the first parasitic capacitor CAP1 is charged by a voltage supply via the first switch Q1. Then, the second parasitic capacitor CAP2 discharges the charges, which flows away through the fourth switch Q4. The charges discharged from the second parasitic capacitor CAP2 cannot be utilized in the process of charging the first parasitic capacitor CAP1, and are thus wasted.